1. Field of the Invention
The present invention generally relates to the formation of an electrical connection between trench capacitors and semiconductor transistors and more specifically to an improved method of forming a buried strap to make such an electrical connection.
2. Description of the Related Art
Trench storage cells are used in dynamic random access memory (DRAM) products due to the high degree of planarity obtainable with the trench structure during chip processing. One of the challenges associated with trench DRAM processing is the formation of an electrical connection between the trench capacitor and the diffusion region of the array device pass transistor.
Conventionally, as shown in FIG. 1F, a "buried strap" 120 connection is made between the top of the trench 100 and the diffusion region (i.e., drain 134) of the transistor 130. The buried strap 120 connection eliminates the requirement for a distinct lithographic patterning level. However, multiple polysilicon deposition, planarization, and etch recess steps are required to form the buried strap 120.
More specifically, the conventional process of forming a buried strap is illustrated in FIGS. 1A-1F. FIG. 1A illustrates a trench 100 which is formed in a substrate 101 and a pad silicon nitride 104 by conventional means such as photolithography and dry etching using a mixture of gases which may include Cl.sub.2, Hbr, O.sub.2, N.sub.2, and NF.sub.3 to a depth of 2 .mu.m-1.5 .mu.m below the pad nitride using dry etching and a mixture of gasses which may include SF.sub.6, CF.sub.4, O.sub.2, and N.sub.2. Then a collar dielectric oxide 103 (such as silicon dioxide or silicon oxynitride) is deposited over the pad nitride 104 and trench 100.
As shown in FIG. 1B, the collar oxide is etched in an anisotropic dry etch process such as reactive ion etching (RIE) using a mixture of gases which may include some portions of CHF3, Ar, 02, C4F8, and CO. The anisotropic dry etch, or sidewall spacer etch, removes material in a vertical direction at a high rate, but removes material in the horizontal direction at a relatively low rate. Therefore, the high selectivity anisotropic spacer etch will leave material along the sidewall of the trenches, and remove material from the horizontal surfaces.
As shown in FIG. 1C, the trench is then filled with a second level of polysilicon 110. The second level of polysilicon is then recessed to a depth of 0.1 .mu.m to 0.5 .mu.m using a dry etch. Then, as shown in FIG. 1D, the collar oxide is etched down to the level of the second level of polysilicon 110 using a wet etch such as Hf.
A third level of polysilicon 120 is deposited and the structure is planarized and recessed below the pad nitride 104 using a dry etch process, as shown in FIG. 1E. The third level of polysilicon 120 becomes the strap which contacts the diffusion area of the transistor.
The structure shown in FIG. 1E is formed in conjunction with a transistor 130, such as a metal oxide semiconductor field effect transistor (MOSFET), which is illustrated in FIG. 1F. More specifically, the transistor includes a gate 131, a gate oxide 132, a source region 133, a drain region 134 and shallow trench isolation (STI) region 135. The process of forming the transistor 130 is well known to those ordinarily skilled in the art and will not be discussed herein for the sake of brevity.
The third level of polysilicon 120 comprises a strap and forms an electrical connection between the first and second layers of polysilicon 102, 110 and the drain 134 of the transistor 130. This type of strap is known as a buried strap because it exists below the top surface of the substrate 101. By utilizing such a buried strap, the size of the semiconductor device can be reduced and, since an external strap is not required, the chance of damage to other structures within the semiconductor device is also reduced.
However, as explained above, at least three polysilicon deposition and etching steps are required with the conventional process. This increases the cost of producing such a structure. Further, because of the multiplicity of steps required, the chance for error or contamination increases with each additional processing step. Therefore, the defect rate of the conventional process is excessive. Therefore, there is a long felt need to reduce the complexity, and cost, of the process used to manufacture the buried strap connection between the trench capacitor and the transistor.